module InstMemory(clk, MemWrite, Address, WriteData, ReadData);

input clk, MemWrite;
 input [6:2] Address;
 input [31:0] WriteData;
 output [31:0] ReadData;
wire NotMemWrite;
wire [31:0] pReadData, nReadData, Extended_MemWrite, nExtended_MemWrite;
//memory
wire [31:0] InstReg1,
InstReg2,
InstReg3,
InstReg4,
InstReg5,
InstReg6,
InstReg7,
InstReg8,
InstReg9,
InstReg10,
InstReg11,
InstReg12,
InstReg13,
InstReg14,
InstReg15,
InstReg16,
InstReg17,
InstReg18,
InstReg19,
InstReg20,
InstReg21,
InstReg22,
InstReg23,
InstReg24,
InstReg25,
InstReg26,
InstReg27,
InstReg28,
InstReg29,
InstReg30,
InstReg31,
InstReg32
;
assign InstReg1 = 32'h0001;
//-----------for write variable-----------//
wire [31:0] DecodedAddr, MWonDecAddr;
wire [31:0] SelInstReg1,
SelInstReg2,
SelInstReg3,
SelInstReg4,
SelInstReg5,
SelInstReg6,
SelInstReg7,
SelInstReg8,
SelInstReg9,
SelInstReg10,
SelInstReg11,
SelInstReg12,
SelInstReg13,
SelInstReg14,
SelInstReg15,
SelInstReg16,
SelInstReg17,
SelInstReg18,
SelInstReg19,
SelInstReg20,
SelInstReg21,
SelInstReg22,
SelInstReg23,
SelInstReg24,
SelInstReg25,
SelInstReg26,
SelInstReg27,
SelInstReg28,
SelInstReg29,
SelInstReg30,
SelInstReg31,
SelInstReg32
;

//Select instruction
MUX32to1_32bit mux1(
InstReg1,
InstReg2,
InstReg3,
InstReg4,
InstReg5,
InstReg6,
InstReg7,
InstReg8,
InstReg9,
InstReg10,
InstReg11,
InstReg12,
InstReg13,
InstReg14,
InstReg15,
InstReg16,
InstReg17,
InstReg18,
InstReg19,
InstReg20,
InstReg21,
InstReg22,
InstReg23,
InstReg24,
InstReg25,
InstReg26,
InstReg27,
InstReg28,
InstReg29,
InstReg30,
InstReg31,
InstReg32,
  pReadData[31:0],
  Address[6:2]
);
//clk in -> output

assign NotMemWrite= ~MemWrite;
Register_32bit reg32(
  clk,
  1'b1,
  pReadData[31:0],
  ReadData[31:0],
  {NotMemWrite, NotMemWrite}
 );

//-------------------------under this line, code for write------------------------//

DECODER_5bit Dec1(Address[6:2], DecodedAddr[31:0]);
Extend_32bit Ext1(MemWrite, Extended_MemWrite[31:0]);
and_32bit a1(Extended_MemWrite[31:0], DecodedAddr[31:0], MWonDecAddr[31:0]);
and_32bit_extI2 a2(WriteData[31:0], DecodedAddr[0], SelInstReg1[31:0]);
and_32bit_extI2 a3(WriteData[31:0], DecodedAddr[1], SelInstReg2[31:0]);
and_32bit_extI2 a4(WriteData[31:0], DecodedAddr[2], SelInstReg3[31:0]);
and_32bit_extI2 a5(WriteData[31:0], DecodedAddr[3], SelInstReg4[31:0]);
and_32bit_extI2 a6(WriteData[31:0], DecodedAddr[4], SelInstReg5[31:0]);
and_32bit_extI2 a7(WriteData[31:0], DecodedAddr[5], SelInstReg6[31:0]);
and_32bit_extI2 a8(WriteData[31:0], DecodedAddr[6], SelInstReg7[31:0]);
and_32bit_extI2 a9(WriteData[31:0], DecodedAddr[7], SelInstReg8[31:0]);
and_32bit_extI2 a10(WriteData[31:0], DecodedAddr[8], SelInstReg9[31:0]);
and_32bit_extI2 a11(WriteData[31:0], DecodedAddr[9], SelInstReg10[31:0]);
and_32bit_extI2 a12(WriteData[31:0], DecodedAddr[10], SelInstReg11[31:0]);
and_32bit_extI2 a13(WriteData[31:0], DecodedAddr[11], SelInstReg12[31:0]);
and_32bit_extI2 a14(WriteData[31:0], DecodedAddr[12], SelInstReg13[31:0]);
and_32bit_extI2 a15(WriteData[31:0], DecodedAddr[13], SelInstReg14[31:0]);
and_32bit_extI2 a16(WriteData[31:0], DecodedAddr[14], SelInstReg15[31:0]);
and_32bit_extI2 a17(WriteData[31:0], DecodedAddr[15], SelInstReg16[31:0]);
and_32bit_extI2 a18(WriteData[31:0], DecodedAddr[16], SelInstReg17[31:0]);
and_32bit_extI2 a19(WriteData[31:0], DecodedAddr[17], SelInstReg18[31:0]);
and_32bit_extI2 a20(WriteData[31:0], DecodedAddr[18], SelInstReg19[31:0]);
and_32bit_extI2 a21(WriteData[31:0], DecodedAddr[19], SelInstReg20[31:0]);
and_32bit_extI2 a22(WriteData[31:0], DecodedAddr[20], SelInstReg21[31:0]);
and_32bit_extI2 a23(WriteData[31:0], DecodedAddr[21], SelInstReg22[31:0]);
and_32bit_extI2 a24(WriteData[31:0], DecodedAddr[22], SelInstReg23[31:0]);
and_32bit_extI2 a25(WriteData[31:0], DecodedAddr[23], SelInstReg24[31:0]);
and_32bit_extI2 a26(WriteData[31:0], DecodedAddr[24], SelInstReg25[31:0]);
and_32bit_extI2 a27(WriteData[31:0], DecodedAddr[25], SelInstReg26[31:0]);
and_32bit_extI2 a28(WriteData[31:0], DecodedAddr[26], SelInstReg27[31:0]);
and_32bit_extI2 a29(WriteData[31:0], DecodedAddr[27], SelInstReg28[31:0]);
and_32bit_extI2 a30(WriteData[31:0], DecodedAddr[28], SelInstReg29[31:0]);
and_32bit_extI2 a31(WriteData[31:0], DecodedAddr[29], SelInstReg30[31:0]);
and_32bit_extI2 a32(WriteData[31:0], DecodedAddr[30], SelInstReg31[31:0]);
and_32bit_extI2 a33(WriteData[31:0], DecodedAddr[31], SelInstReg32[31:0]);

Register_32bit reg01(
  clk,
  1'b1,
  SelInstReg1[31:0],
  InstReg1[31:0],
  {MWonDecAddr[0], MWonDecAddr[0]}
 );

Register_32bit reg1(
  clk,
  1,
  SelInstReg2[31:0],
  InstReg2[31:0],
  {MWonDecAddr[1], MWonDecAddr[1]}
 );
Register_32bit reg2(
  clk,
  1,
  SelInstReg3[31:0],
  InstReg3[31:0],
  {MWonDecAddr[2], MWonDecAddr[2]}
 );
Register_32bit reg3(
  clk,
  1,
  SelInstReg4[31:0],
  InstReg4[31:0],
  {MWonDecAddr[3], MWonDecAddr[3]}
 );
Register_32bit reg4(
  clk,
  1,
  SelInstReg5[31:0],
  InstReg5[31:0],
  {MWonDecAddr[4], MWonDecAddr[4]}
 );
Register_32bit reg5(
  clk,
  1,
  SelInstReg6[31:0],
  InstReg6[31:0],
  {MWonDecAddr[5], MWonDecAddr[5]}
 );
Register_32bit reg6(
  clk,
  1,
  SelInstReg7[31:0],
  InstReg7[31:0],
  {MWonDecAddr[6], MWonDecAddr[6]}
 );
Register_32bit reg7(
  clk,
  1,
  SelInstReg8[31:0],
  InstReg8[31:0],
  {MWonDecAddr[7], MWonDecAddr[7]}
 );
Register_32bit reg8(
  clk,
  1,
  SelInstReg9[31:0],
  InstReg9[31:0],
  {MWonDecAddr[8], MWonDecAddr[8]}
 );
Register_32bit reg9(
  clk,
  1,
  SelInstReg10[31:0],
  InstReg10[31:0],
  {MWonDecAddr[9], MWonDecAddr[9]}
 );
Register_32bit reg10(
  clk,
  1,
  SelInstReg11[31:0],
  InstReg11[31:0],
  {MWonDecAddr[10], MWonDecAddr[10]}
 );
Register_32bit reg11(
  clk,
  1,
  SelInstReg12[31:0],
  InstReg12[31:0],
  {MWonDecAddr[11], MWonDecAddr[11]}
 );
Register_32bit reg12(
  clk,
  1,
  SelInstReg13[31:0],
  InstReg13[31:0],
  {MWonDecAddr[12], MWonDecAddr[12]}
 );
Register_32bit reg13(
  clk,
  1,
  SelInstReg14[31:0],
  InstReg14[31:0],
  {MWonDecAddr[13], MWonDecAddr[13]}
 );
Register_32bit reg14(
  clk,
  1,
  SelInstReg15[31:0],
  InstReg15[31:0],
  {MWonDecAddr[14], MWonDecAddr[14]}
 );
Register_32bit reg15(
  clk,
  1,
  SelInstReg16[31:0],
  InstReg16[31:0],
  {MWonDecAddr[15], MWonDecAddr[15]}
 );
Register_32bit reg16(
  clk,
  1,
  SelInstReg17[31:0],
  InstReg17[31:0],
  {MWonDecAddr[16], MWonDecAddr[16]}
 );
Register_32bit reg17(
  clk,
  1,
  SelInstReg18[31:0],
  InstReg18[31:0],
  {MWonDecAddr[17], MWonDecAddr[17]}
 );
Register_32bit reg18(
  clk,
  1,
  SelInstReg19[31:0],
  InstReg19[31:0],
  {MWonDecAddr[18], MWonDecAddr[18]}
 );
Register_32bit reg19(
  clk,
  1,
  SelInstReg20[31:0],
  InstReg20[31:0],
  {MWonDecAddr[19], MWonDecAddr[19]}
 );
Register_32bit reg20(
  clk,
  1,
  SelInstReg21[31:0],
  InstReg21[31:0],
  {MWonDecAddr[20], MWonDecAddr[20]}
 );
Register_32bit reg21(
  clk,
  1,
  SelInstReg22[31:0],
  InstReg22[31:0],
  {MWonDecAddr[21], MWonDecAddr[21]}
 );
Register_32bit reg22(
  clk,
  1,
  SelInstReg23[31:0],
  InstReg23[31:0],
  {MWonDecAddr[22], MWonDecAddr[22]}
 );
Register_32bit reg23(
  clk,
  1,
  SelInstReg24[31:0],
  InstReg24[31:0],
  {MWonDecAddr[23], MWonDecAddr[23]}
 );
Register_32bit reg24(
  clk,
  1,
  SelInstReg25[31:0],
  InstReg25[31:0],
  {MWonDecAddr[24], MWonDecAddr[24]}
 );
Register_32bit reg25(
  clk,
  1,
  SelInstReg26[31:0],
  InstReg26[31:0],
  {MWonDecAddr[25], MWonDecAddr[25]}
 );
Register_32bit reg26(
  clk,
  1,
  SelInstReg27[31:0],
  InstReg27[31:0],
  {MWonDecAddr[26], MWonDecAddr[26]}
 );
Register_32bit reg27(
  clk,
  1,
  SelInstReg28[31:0],
  InstReg28[31:0],
  {MWonDecAddr[27], MWonDecAddr[27]}
 );
Register_32bit reg28(
  clk,
  1,
  SelInstReg29[31:0],
  InstReg29[31:0],
  {MWonDecAddr[28], MWonDecAddr[28]}
 );
Register_32bit reg29(
  clk,
  1,
  SelInstReg30[31:0],
  InstReg30[31:0],
  {MWonDecAddr[29], MWonDecAddr[29]}
 );
Register_32bit reg30(
  clk,
  1,
  SelInstReg31[31:0],
  InstReg31[31:0],
  {MWonDecAddr[30], MWonDecAddr[30]}
 );
Register_32bit reg31(
  clk,
  1,
  SelInstReg32[31:0],
  InstReg32[31:0],
  {MWonDecAddr[31], MWonDecAddr[31]}
 );

endmodule
